Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 191)

Rev.2.10 Apr 14, 2006 page 167 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface

Item Specification

Transfer data format • Character bit (transfer data): Selectable from 7, 8 or 9 bits

• Start bit: 1 bit

• Parity bit: Selectable from odd, even, or none

• Stop bit: Selectable from 1 or 2 bits

Transfer clock • CKDIR bit in UiMR register = 0 (internal clock) : fj/(16(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

• The CKDIR bit = 1 (external clock) : fEXT/(16(n+1))

fEXT: Input from CLKi pin. n :Setting value of the UiBRG register 00h to FFh

Transmit/receive control

_______ _______ _______ _______

Selectable from CTS function, RTS function or CTS/RTS function disabled

Transmit start condition Before transmission can start, meet the following requirements

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in UiTB register)

•

_______ ________

If CTS function is selected, input on the CTSi pin = L

Receive start condition Before reception can start, meet the following requirements

• The RE bit in the UiC1 register = 1 (reception enabled)

• Start bit detection

Interrupt request For transmission, one of the following conditions can be selected

generation timing • The UiIRS bit

(1)

= 0 (transmit buffer empty): when transferring data from the UiTB register

to the UARTi transmit register (at start of transmission)

• The UiIRS bit =1 (transmission completed): when the serial interface finished

transmitting data from the UARTi transmit register

For reception

• When transferring data from the UARTi receive register to the UiRB register

(at completion of reception)

Error detection • Overrun error

(2)

This error occurs if the serial interface started receiving the next data before reading

the UiRB register and received the bit one before the last stop bit of the next data

• Framing error

(3)

This error occurs when the number of stop bits set is not detected

• Parity error

(3)

This error occurs when if parity is enabled, the number of 1’s in parity and character

bits does not match the number of 1’s set

• Error sum flag

This flag is set to 1 when any of the overrun, framing, or parity errors occur

Select function • LSB first, MSB first selection

Whether to start transmitting or receiving data begins with bit 0 or begins with bit 7 can

be selected

• Serial data logic switch

This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed.

• TXD, RXD I/O polarity switch

This function reverses the polarities of the TXD pin output and RXD pin input.

The logic levels of all I/O data is reversed.

•

_______ _______

Separate CTS/RTS pins (UART0)

_________ _________

CTS0 and RTS0 are input/output from separate pins

15.1.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data

format. Table 15.5 lists the UART Mode Specifications. Table 15.6 lists the Registers to be Used and

Setting in UART Mode.

Table 15.5 UART Mode Specifications

i = 0 to 2

NOTES:

1. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.

2. If an overrun error occurs, the receive data of UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged.

3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the

UARTi receive register to the UiRB register.

1 2 ... 186 187 188 189 190 191 192 193 194 195 196 ... 411 412

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