Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 202)

Rev.2.10 Apr 14, 2006 page 178 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface

No acknowledgment detection

(NACK)

Rising edge of SCLi 9th bit

Acknowledgment detection (ACK)

Rising edge of SCLi 9th bit

Acknowledgment detection (ACK)

UARTi transmission

Falling edge of

SCLi next to the

9th bit

Falling and rising

edges of SCLi 9th

bit

1st to 8th bits are

stored into bit 7 to bit

0 in UiRB register

(3)

Bit 6 to bit 0 in the UiRB

(4)

are read as bit

7 to bit 1. Bit 8 in the UiRB

UARTi transmission

Rising edge of

SCLi 9th bit

Falling edge of

SCLi 9th bit

Table 15.12 I

C Mode Functions

i = 0 to 2

NOTES:

1. If the interrupt source is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to

1 (interrupt requested). (Refer to 23.8 Interrupts.)

If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to set

the IR bit to 0 (interrupt not requested) after changing those bits.

• Bits SMD2 to SMD0 in UiMR register • IICM bit in UiSMR register

• IICM2 bit in UiSMR2 register • CKPH bit in UiSMR3 register

2. Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register = 000b (serial interface disabled).

3. Second data transfer to the UiRB register (rising edge of SCLi 9th bit)

4. First data transfer to the UiRB register (falling edge of SCLi 9th bit)

5. See Figure 15.26 STSPSEL Bit Functions.

6. See Figure 15.24 Transfer to UiRB Register and Interrupt Timing.

7. When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to 1 (interrupt source: UART0 bus collision detection).

When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to 1 (interrupt source: UART1 bus collision detection).

Function

Clock

Synchronous

Serial I/O Mode

(SMD2 to SMD0 =

001b, IICM = 0)

C Mode (SMD2 to SMD0 = 010b, IICM = 1)

IICM2 = 0

(NACK/ACK interrupt)

IICM2 = 1

(UART transmit/receive interrupt)

CKPH = 0

(No clock delay)

CKPH = 1

(Clock delay)

Source of interrupt

number 6, 7, and

(1) (5) (7)

Source of interrupt

number 15, 17, and

(1) (6)

Source of interrupt

number 16, 18, and

(1) (6)

Timing for transferring

data from UART

reception shift register

to UiRB register

UARTi transmission

output delay

Functions of pins

P6_3, P6_7, and P7_0

Functions of pins

P6_2, P6_6, and P7_1

Functions of pins

P6_1, P6_5, and P7_2

Noise filter width

Read RXDi and

SCLi pins levels

Initial value of TXDi

and SDAi outputs

Initial and end

value of SCLi

DMA1 source

(6)

Store received

data

Read received

data

UARTi transmission

Transmission started

or completed

(selected by UiIRS)

UARTi reception

When 8th bit received

CKPOL = 0 (rising edge)

CKPOL = 1 (falling edge)

CKPOL = 0 (rising edge)

CKPOL = 1 (falling edge)

Not delayed

TXDi output

RXDi input

CLKi input or

output selected

15 ns

Possible when the

corresponding port

direction bit = 0

CKPOL = 0 (H)

CKPOL = 1 (L)

UARTi reception

The UiRB register status is read

CKPH = 0

(No clock delay)

CKPH = 1

(Clock delay)

1st to 8th bits of the received data are stored into bits

7 to 0 in the UiRB register

Start condition detection or stop condition detection

(See Table 15.13 STSPSEL Bit Functions)

UARTi reception

Falling edge of SCLi 9th bit

Delayed

SDAi input/output

SCLi input/output

- (Cannot be used in I

C mode)

200 ns

Always possible no matter how the corresponding port direction bit is set

The value set in the port register before setting I

C mode

(2)

UARTi reception

Falling edge of SCLi 9th bit

1st to 7th bits of the received data are stored into

bits 6 to 0 in the UiRB

bit 8 in the UiRB register

1 2 ... 197 198 199 200 201 202 203 204 205 206 207 ... 411 412

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