Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 272)

Rev.2.10 Apr 14, 2006 page 248 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports

20.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13)

Figure 20.7 shows the PDi Register.

This register selects whether the I/O port is to be used for input or output. The bits in this register correspond

one for one to each port.

During memory expansion and microprocessor modes

(1)

, the PDi registers for the pins functioning as bus

_______ _______ _____ ________ ______ _________ ________ ________ __________ __________

control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and

BCLK) cannot be modified.

No direction register bit for P8_5 is available.

NOTE:

1. Not available memory expansion and microprocessor modes in T/V-ver..

20.2 Pi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13), PC14 Register

Figure 20.8 shows the Pi Register.

Data input/output to and from external devices are accomplished by reading and writing to the Pi register.

The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For

ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and

data can be written to the port latch by writing to the Pi register.

For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data

can be written to the port latch by writing to the Pi register. The data written to the port latch is output from

the pin. The bits in the Pi register correspond one for one to each port.

During memory expansion and microprocessor modes

(1)

, the Pi registers for the pins functioning as bus

_______ _______ _____ ________ ______ _________ ________ ________ __________ __________

control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and

BCLK) cannot be modified.

About the port P14 (128-pin version), Figure 20.8 shows the PC14 Register.

NOTE:

1. Not available memory expansion and microprocessor modes in T/V-ver..

20.3 PURj Register (100-pin Version: j = 0 to 2, 128-pin Version: j = 0 to 3)

Figures 20.9 and 20.10 show the PURj Register.

The PURj register bits can be used to select whether or not to pull the corresponding port high in 4-bit unit.

The port selected to be pulled high has a pull-up resistor connected to it when the direction bit is set for input

mode.

However, the pull-up control register has no effect on P0 to P3, P4_0 to P4_3, and P5 during memory

expansion and microprocessor modes

(1)

. Although the register contents can be modified, no pull-up resistors

are connected.

When using the ports P11 to P14, set the PUR37 bit in the PUR3 register to 1 (P11 to P14 are usable).

NOTE:

1. Not available memory expansion and microprocessor modes in T/V-ver..

20.4 PCR Register

Figure 20.11 shows the PCR Register.

When the P1 register is read after setting the PCR0 bit in the PCR register to 1, the corresponding port latch

can be read no matter how the PD1 register is set.

Table 20.2 lists the Unassigned Pin Handling in Single-chip Mode and Table 20.3 lists the Unassigned Pin

Handling in Memory Expansion Mode and Microprocessor Mode (normal-ver. only).

Figure 20.12 shows the Unassigned Pin Handling.

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