Renesas M16C/6NK Informações Técnicas descarregar pdf (Página 199)

Rev.2.10 Apr 14, 2006 page 175 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface

15.1.3 Special Mode 1 (I

C Mode)

C mode is provided for use as a simplified I

C interface compatible mode. Table 15.10 lists the I

C Mode

Specifications. Figure 15.23 shows the I

C Mode Block Diagram. Table 15.11 lists the Registers to be

Used and Setting in I

C Mode. Table 15.12 lists the I

C Mode Functions. Figure 15.24 shows the Transfer

to UiRB Register and Interrupt Timing.

As shown in Table 15.12, the MCU is placed in I

C mode by setting bits SMD2 to SMD0 to 010b and the

IICM bit to 1. Because SDAi transmit output has a delay circuit attached, SDAi output does not change

state until SCLi goes low and remains stably low.

Table 15.10 I

C Mode Specifications

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock • During master

The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

• During slave

The CKDIR bit = 1 (external clock) : Input from SCLi pin

Transmit start condition Before transmission can start, meet the following requirements

(1)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Receive start condition Before reception can start, meet the following requirements

(1)

• The RE bit in the UiC1 register = 1 (reception enabled)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

When start or stop condition is detected, acknowledge undetected, and acknowledge

detected

Error detection Overrun error

(2)

This error occurs if the serial I/O started receiving the next data before reading the

UiRB register and received the 8th bit of the next data

Select function • Arbitration lost

Timing at which the ABT bit in the UiRB register is updated can be selected

• SDAi digital delay

No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable

• Clock phase setting

With or without clock delay selectable

Interrupt request

generation timing

i = 0 to 2

NOTES:

1. When an external clock is selected, the conditions must be met while the external clock is in the high state.

2. If an overrun error occurs, the value of UiRB register will be undefined. The IR bit in the SiRIC register

remains unchanged.

1 2 ... 194 195 196 197 198 199 200 201 202 203 204 ... 411 412

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